Augmenting an electronic Ising machine to effectively solve boolean satisfiability

With the slowdown of improvement in conventional von Neumann systems, increasing attention is paid to novel paradigms such as Ising machines. They have very different approach to solving combinatorial optimization problems. Ising machines have shown great potential in solving binary optimization problems like MaxCut. In this paper, we present an analysis of these systems in boolean satisfiability (SAT) problems. We demonstrate that, in the case of 3-SAT, a basic architecture fails to produce meaningful acceleration, largely due to the relentless progress made in conventional SAT solvers. Nevertheless, careful analysis attributes part of the failure to the lack of two important components: cubic interactions and efficient randomization heuristics. To overcome these limitations, we add proper architectural support for cubic interaction on a state-of-the-art Ising machine. More importantly, we propose a novel semantic-aware annealing schedule that makes the search-space navigation much more efficient than existing annealing heuristics. Using numerical simulations, we show that such an “Augmented” Ising Machine for SAT is projected to outperform state-of-the-art software-based, GPU-based and conventional hardware SAT solvers by orders of magnitude.

The coupling unit includes two programmable resistors and a pair of switches.To enable positive coupling, S + i j is closed, connecting OUT i to IN + j through a programmable resistor.To enable negative coupling, S − i j is closed, which connects OUT i to IN − j .S + i j and S − i j are mutually exclusive, only one can be closed at a time for the circuit to operate as intended.Implementing resistors directly on-chip is costly in terms of area and does not allow for programmable values to account for different coupling strengths between nodes.To circumvent both of these issues, rather than using a physical resistor, two p-type transistors are connected with a capacitor across the source and gate as shown in Fig. S1 [Right].This configuration has a similar I-V characteristic to a physical resistor while consuming less area.By setting the voltage (V ctr ) across the capacitor, the effective resistance can be tuned, allowing for programmable resistances.
The node design in Fig. S2 includes a capacitor, which stores the current state of the node, and a buffer to quantize the output to either V SS or V DD .The node takes two inputs, i + re f and i − re f , which are currents due to positive and negative couplings respectively.The current i + re f is mirrored as i + flowing from V DD to the positive plate of the capacitor, thus charging it.Whereas, i − re f is mirrored as i − such that it flows out of the positive plate to ground, thus discharging the capacitor.Therefore, the net current flowing into the positive plate of the capacitor is (i + − i − ).With this arrangement, more positive couplings would result in charging the capacitor while the capacitor will discharge if there are more negative couplings.
We tested the Cadence implementation with a fully-connected 6-node MaxCut graph using all possible initial states.The system settled into a local minimum for every possible input, with an average power draw of 200 µW .Preliminary analysis revealed that the power consumption scales with the number of active coupling units and the number of nodes at V DD .Taking into account the cubic couplings, couplings to generate M n and TMB hardware in AIMS, a 500-variable SAT problem is Supplementary Figure S2.Circuit architecture of a node.The node consists of two current mirrors (left), a capacitor, and a buffer to quantize the voltage (right).estimated to consume ∼ 300 mW power and require ∼ 13 × 13 mm 2 chip area.
Illustrative example of M n , B n and TMB a b Current assignment: For $ " : Fig. S3a shows an example illustration of M n and B n for the variable x 4 in formula F. With the shown current assignment, if variable x 4 is selected to be flipped, it will satisfy 3 new clauses (M 4 = 3) C8, C9 and C11, however, 1 new clause (B 4 = 1) C18 will be unsatisfied.
Fig. S3b shows the function p n in TMB as M n and B n varies for a tuned c m and c b .We can observe that probability of flipping a node increases when M n increases and B n decreases.In other words, the system stochastically flips variables that are are involved in more unsatisfied clauses and fewer break clauses.

Relation between M n , B n and the dynamics of cBRIM
Let us consider the Hamiltonian (H n ) of only those clauses, Without loss of generality, let us consider literal ℓ i1 to be associated with variable x n .After expanding H n , for each clause C i , we focus only on the terms containing x n , referred to as T i|x n .
We define C i to be x n -UNSAT if and only if subclause (ℓ i2 ∨ ℓ i3 ) is unsatisfied.Suppose that C i contains x n .Using the definition of g(ℓ i j ) in Eq. 1, if C i is x n -UNSAT, then T i|x n = −1 and 0 otherwise.On the contrary, if C i contains the negated literal ¬x n , then T i|x n = 1 in the case that C i is x n -UNSAT.We now connect these definitions with the concepts of M n and B n .A key observation is that C i contributes to M n or B n if and only if it is x n -UNSAT.If x n = 1, then all clauses with T i|x n = 1 has ℓ i1 = ¬x n = 0. Thus, such clauses will contribute to M n .While all clauses with T i|x n = −1 contribute to B n .Similarly, if x n = 0, then all clauses with T i|x n = −1 are counted in M n , and all clauses with T i|x n = 1 are counted in B n .To summarize: Moreover, T i|x n is only derived from terms containing x n .This implies, ∂ H ∂ v n = ∑ i|x n ∈C i T i|x n .Therefore, the differential equation for AIMS becomes: Hardware implementation of TMB With M n and B n represented as currents, we can design a circuit to compute p n for TMB with approximate tanh generators and using an AND gate to approximate the multiplication.Fig. S4 shows an example implementation.The current R \n is generated using coupling units not shown in the figure.Based on the quantized state of the node x n , a switch is set to ensure the current flowing into the (1 − tanh) circuit is always B n and also to get M n from R \n .The tanh function is implemented by modifying a differential current-mode implementation shown in a recent work 1 .The resulting circuit is shown in Fig. S5.Using this, (1 − tanh) is trivial to implement as shown in the zoomed-in part of Fig. S4.The parameters c m and c b are tuned by applying a gain to the current-controlled current source that mirrors the input current in the tanh circuit.The output currents of the tanh and (1 − tanh) circuits, referred to as I s and I t , are used to control the current-controlled voltage sources V s and V t respectively.Note that, I s , I t ∈ [0, I bias ] because the input currents, M n and B n are positive.V s and V t produce voltages in the range [0,V DD ] which are fed as inputs to an AND gate to multiply approximately.The output of AND gate controls the S5.CMOS implementation of a single-ended tanh circuit.probability p n of a stochastic circuit that outputs V out = 1 with a probability p n .This way, each node can be selected by our TMB heuristic to flip if V out = 1.With this circuit, we measure a delay of 1 ns in Cadence simulation to select a node to flip.
While the TMB heuristic requires extra hardware, it is only needed per node and thus comes with O(N) cost.The system's overall circuit complexity is dominated by that of the O(N 2 ) couplers.

Generating M n
Let us consider the Hamiltonian (H n ) of only those clauses (C i ) involving node n (variable x n ).This function has some terms that contain v n (we call them collectively R n ) and the remaining that do not (R \n ).
A simple but key insight of the nature of H n is that, a clause C i is unsatisfied if and only if the product g(ℓ i1 )g(ℓ i2 )g(ℓ i3 ) = 1.Otherwise, C i is satisfied with the product being 0. Therefore, H n = M n .We know that, the incoming current of each node is simply dv n dt = −α ∂ R n ∂ v n .This is because only R n contains terms with v n .Using this fact in Eq. 5, where x n is the quantized state of the node.While deriving Eq. 6, we use a simplification that since x n ∈ {0, 1}, we can write x 2 n = x n .The first term in Eq. 6 can be obtained from the incoming current and only contributes when x n = 1.The second term (R \n ) can be computed by generating an electric current just like the regular coupling units.As a result, we generate a current proportional to M n .

Impact of clamp time on AIMS
In a fast dynamical system like AIMS, stochastically flipping a node with TMB heuristic is achieved by clamping the node to a fixed polarity using a large current driver for a specific duration.Assuming the system started in a fixed point (local minimum), too short and too few of these clampings will almost certainly result in the voltages reverting back quickly to the prior value.By its very nature, our design flips nodes in an asynchronous manner and allows multiple stochastically overlapping flips.Lengthening the duration increases the number of overlaps.Fig. S6a shows the success probability of AIMS while solving 20 different 500-variable problems with constant annealing time of 0.44 ms and increasing node clamp time.From the figure, we can observe that too short clamp times result in poor solution quality.In this case, we conjecture that the system may not get Table S1 shows the hardware parameters of existing Ising machines compared to this work.Some key points to note: 1) Majority of Ising machines do not support high-degree interactions.2) Most Ising machines only support sparse hardware topology thus limiting its usability.3) Although our proposed Ising machine takes more chip area, to the best of our knowledge, it is the only one projected to outperform state-of-the-art SAT solvers by orders of magnitude.
The reported power consumption for the ISSCC 2020 work is the measured peak power while solving an all-to-all connected MaxCut graph.In contrast, AIMS targets 3-SAT problems which are very sparse (∼2% density).This implies that majority (98%) of the coupling units in AIMS are switched off leading to much lower power consumption.
Visualization of TMB.a) Example illustration of make count (M n ) and break count (B n ) for the variable x 4 .Clauses are numbered C1 to C21 with green indicating satisfied and red indicating unsatisfied with the current assignment.b) 3D Plot of p n as a function of M n and B n for a tuned c m and c b value.
Supplementary FigureS4.The CMOS circuit implementation of the heuristic.